View LC7074M_287836.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Ordering number:ENN4789
CMOS IC
LC7074, 7074M
Synchronous Error Correction IC for RDS Applications
Overview
The LC7074 and the LC7074M are ICs for the RDS (radio data system) implemented by the EBU (European Broadcasting Union) and the RDBS (radio broadcast data system) implemented by the NRSC (National Radio System Committee) in the USA. RDS and RBDS are standards that allow data to be broadcast multiplexed with other FM broadcasts. When combined with an IC in the LA2230 series, the LC7074/M synchronizes with data multiplexed in an FM broadcast and detects and corrects errors in that data. The synchronized data is output as a serial signal which can then be decoded and processed on the system control microprocessor.
Package Dimensions
unit:mm 3007B-DIP18
[LC7074]
24.0 18 10
7.62 6.4
1
9
Functions
* Group synchronization. RDS group synchronization. MMBS/RDS group synchronization. * Error detection and correction. * Error detection function enable/disable selection. * Serial data output. * Serial data clock polarity selection. * Data block start signal output.
(1.84) 2.54 0.5 1.2
0.51min
SANYO : DIP18
unit:mm 3095-MFP18
[LC7074M]
18 10
Features
* System that decode, synchronize and detect and correct errors can easily be constructed by combining the LC7074/M with an LA2230 series product. * Reduces overhead in the microprocessor that decodes and processes the RDS or MMBS/RDS data. Product-Package Relationship
Product No. LC7074 LC7074M DIP18 MFP18 Package 0.35 1.27 6.35 7.6 5.4
12.6
1.22
0.1 1.5
SANYO : MFP18
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
80101TN (KT)/12094JN B8-0839 * 0840 No.4789-1/17
0.625
1
9
1.8max
0.15
3.3
3.85max
(3.25)
0.25
LC7074, 7074M
Pin Assignment
The LC7070 Series This section describes the differences between the different products in the LC7070 series Usage Notes This basic functions, including the pin functions and I/O timing, are identical in all products in the series. However, some pin circuits and function operation details differ. * LC7070NM...While the LC7074M is pin compatible with this product, the circuit type of the three output pins differs as shown in table, Package and Output Driver Type Comparison. These products can be interchanged to match the output interface. However, since the data output method following synchronization detection differs as shown in table, Comparison of Functional Differences, care is required in writing programs that receive, decode and process the output data for the control microprocessor. * LC7070N......While the LC7074 is pin compatible with this product, the circuit type of the three output pins differs as shown in table, Package and Output Driver Type Comparison. These products can be interchanged to match the output interface. However, since the data output method following synchronization detection differs as shown in table, Comparison of Functional Differences, care is required in writing programs that receive, decode and process the output data for the control microprocessor. * LC7071NM...The LC7074M is pin compatible with this product, and the pin circuit types, pin functions, and signal timings are identical. In principle, these products are interchangeable. However, since the data output method following synchronization detection differs as shown in table, Comparison of Functional Differences, care is required in writing programs that receive, decode and process the output data for the control microprocessor. * LC7073.........The LC7074 is pin compatible with this product, and the pin circuit types, pin functions, and signal timings are identical. Furthermore, the synchronization detection method and the post-synchronization data output method are also identical. In principle, these products are interchangeable. However, since these products handle the block offset words E and F differently, and also handle MMBS/RDS data differently as shown in table, Comparison of Functional Differences, care is required in writing programs that receive, decode and process the output data for the control microprocessor. * LC7073M......The LC7074M is pin compatible with this product, and the pin circuit types, pin functions, and signal timings are identical. Furthermore, the synchronization detection method and the post-synchronization data output method are also identical. In principle, these products are interchangeable. However, since these products handle the block offset words E and F differently, and also handle MMBS/RDS data differently as shown in table, Comparison of Functional Differences, care is required in writing programs that receive, decode and process the output data for the control microprocessor.
No.4789-2/17
LC7074, 7074M
Package and Output Driver Type Comparison
Product No. LC7070N LC7070NM LC7071NM LC7073 LC7073M LC7074 LC7074M Package DIP18 MFP18 MFP18 DIP18 MFP18 DIP18 MFP18 Open drain type Pull-up MOS transistor (CMOS type) Pull-up MOS transistor (CMOS type) Pull-up MOS transistor (CMOS type) See table, Comparison of Functional Differences. See table, Comparison of Functional Differences. Output driver type difference* Function Identical functions
Note: *Only applies to the three pins DATA START, DATA OUT and CLOCK OUT. Comparison of Functional Differences
Item Offset word E Offset word F LC7070N LC7070NM LC7071NM These are taken to be offset words and a group synchronization detection operation is performed. LC7073 LC7073M These are not seen as offset words. Only offset words A, B, C, C' and D are detected. All zero data is not seen as being an offset word E block. Rather, all zero data is taken to mean that there is no input, and synchronization detection is not performed. If all zero data is input, these products decide that data input has stopped, and they stop outputting data and enter the pull-out sequence. Since these products do not synchronize on an offset word E block, each time an RDS group is inserted in an MMBS group, they repeat the pull-out and resynchronization sequences. LC7074 LC7074M Offset words A, B, C, C', D and E are detected. Offset word F is not detected.
All zero data (corresponding to offset E)
All zero data is taken to be an offset word E block. Accordingly, an offset word E block synchronization operation is performed.
All zero data is seen as an offset word E block. Accordingly, an offset word E block synchronization operation is performed.
MMBS/RDS compound data
Synchronization detection method
For the transition from an RDS group (ABCD) to an MMBS group (EEEE) or the reverse transition, these are taken to be the pull-out and resynchronization sequences. During transitions, data errors can occur and data output can be interrupted. Synchronization is achieved when the offset words in five out of 12 blocks are detected in the correct order.
MMBS/RDS data is correctly output with no pull-out and no errors.
Synchronization is achieved when the offset words in two out of three blocks are detected in the correct order.
Post-synchronization detection data
output
When synchronization detection completes with an offset word A block, Data output starts with the data from output starts with the data in the second block (the offset word B block) the first block (the offset word A from the same group. block) in the group following the When synchronization detection completes with an offset word B, C or D group for which synchronization block, output starts with the data in the first block (the offset word A block) detection was completed. from the same group. When the offset words from five or more consecutive blocks were not detected. In modes where error correction is enabled, up to five error bits are corrected for distances of 5 bits or less.
Pull-out determination method Error correction
No.4789-3/17
LC7074, 7074M
Block Diagram
No.4789-4/17
LC7074, 7074M
Pin Functions
Pin VDD, VSS1 VSS2, VSS3 I/O Internal equivalent circuit Power supply Function Value at reset
OSC1 OSC2
I O
Clock oscillator Connect the external ceramic oscillator and capacitor at these pins.
CLOCK IN
I
RDS demodulation clock input Connect to the clock output from the LA2230 series demodulation IC.
DATA IN
I
RDS demodulation data input Connect to the data output from the LA2230 series demodulation IC.
CORR.SEL
I
Error correction selection input This pin selects whether the IC corrects errors in the RDS demodulated data. Input=0: No correction performed* Input=1: Error correction performed In modes where error correction is enabled, up to five error bits are corrected for distances of 5 bits or less. Serial data clock output polarity selection input Input=0: Serial data output is valid on the rising edge of the output clock. (Data output changes on the falling edge of the clock.) Input=1: Serial data output is valid on the falling edge of the output clock. (Data output changes on the rising edge of the clock.)
CL.ED.SEL
I
D.S.CONTROL
I
Block data start signal control input Input=0: Output the DATA START signal for all blocks. Input=1: Output the DATA START signal for only the second block.
RECEIVE
O
RDS data reception in progress output Outputs a low level while serial data is being output following completion of synchronization detection. Outputs a high level at all other times. Open drain output
High level (high impedance)
CORRECTION
O
Error correction operation output Outputs a low level when the serial data output data has been error corrected, or could not be corrected. Outputs a high level (high impedance) when correction is disabled. Open drain output
High level (high impedance)
ERROR
O
Error output Outputs a low level when there were errors in the input data and those errors could not be corrected. Outputs a high level (high impedance) when there were no errors or the errors were corrected. Open drain output
High level (high impedance)
DATA START
O
Serial data output block data start signal The output type is controlled by the D.S.CONTOL input. Pull-up MOS transistor (CMOS) output
High level
Continued on next page.
No.4789-5/17
LC7074, 7074M
Continued from preceding page.
Pin I/O Internal equivalent circuit Function Value at reset
DATA OUT
O
Serial data output data output Pull-up MOS transistor (CMOS) output
High level
CLOCK OUT
O
Serial data output clock output Pull-up MOS transistor (CMOS) output
High level
RES
I
Reset input Input a low level pulse with a length of at least 4 clock cycles to reset and restart IC operation. Note that when a 4 MHz oscillator is used, since a single clock cycle is 0.25s, four clock cycles is 1 s. Schmitt type input. Built-in pull-up resistor
Note: *0: Low level input 1: High level input
Specifications
Electrical Characteristics at Ta = 25C, VSS1, VSS2, VSS3 = 0V
Parameter Supply voltage Output voltage Symbol VDD max VO1 VO2 VI1 Input voltage VI2 IO1 Output current IO2 IO Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD OSC2, DATA START, DATA OUT, CLOCK OUT RECEIVE, CORRECTION, ERROR RES, OSC1: * CLOCK IN, DATA IN, CORR.SEL, CL.ED.SEL, D.S.CONTROL RECEIVE, CORRECTION, ERROR: The output current per pin DATA START, DATA OUT, CLOCK OUT: The output current per pin All output pins: Total value Conditions Ratings - 0.3 to +7.0 - 0.3 to VDD+0.3 - 0.3 to +15 - 0.3 to VDD+0.3 - 0.3 to +15 20 - 2 to +20 - 14 to +90 Up to 250 Up to 150 - 40 to +85 - 55 to +125 Unit V V V V V mA mA mA mW mW
DIP package product: Ta=-40 to +85C MFP package product: Ta=-40 to +85C
C C
Note: *When driving the oscillator with the recommended constants shown in figure 1, values up to the oscillation amplitude that occurs are allowed. Allowable Operating Ranges at Ta = -40 to +85C, VSS1, VSS2, VSS3 = 0V, VDD = 4.5 to 6.0V
Parameter Operating supply voltage Input high-level voltage Symbol VDD VIH1 VIH2 Input low-level voltage Ceramic oscillator guarantee VIL1 VIL2 Conditions VDD CLOCK IN, DATA IN, CORR.SEL. CL.ED.SEL, D.S.CONTROL RES CLOCK IN, DATA IN, CORR.SEL. CL.ED.SEL, D.S.CONTROL RES OSC1, OSC2: See figure 1 Ratings min 4.5 0.7VDD 0.8VDD VSS typ max 6.0 13.5
VDD
Unit V V V V
0.3VDD
0.25VDD V VSS See the ceramic oscillator guaranteed constants table.
No.4789-6/17
LC7074, 7074M
Electrical Characteristics at Ta = -40 to +85C, VSS1, VSS2, VSS3 = 0V, VDD = 4.5 to 6.0V
Parameter Input high-level current Input low-level current Symbol IIH IIL1 IIL2 Output high-level voltage VOH Conditions CLOCK IN, DATA IN, CORR.SEL, CL.ED.SEL, D.S.CONTROL: VIN=13.5V CLOCK IN, DATA IN, CORR.SEL, CL.ED.SEL, D.S.CONTROL: VIN=VSS RES: VIN=VSS DATA START, DATA OUT, CLOCK OUT: IOH=- 50A DATA START, DATA OUT, CLOCK OUT: IOH=- 10A RECEIVE, CORRECTION, ERROR, DATA START, DATA OUT, CLOCK OUT: IOL=10mA RECEIVE, CORRECTION, ERROR, DATA START, DATA OUT, CLOCK OUT: IOL=1.8mA*1 RECEIVE, CORRECTION, ERROR: VO=13.5V RECEIVE, CORRECTION, ERROR: VO=VSS Hysteresis voltage Supply current Ceramic oscillator stabilization time Reset time VHIS IDD tCFS tRST RES
VDD: *2
Ratings min typ max 5.0 - 1.0 - 45
VDD- 1.2
Unit A A
- 10
A V
VDD- 0.5
1.5 V 0.4 5.0 - 1.0 0.1VDD 1.5 See figure 3 3.5 10 V mA ms
Output low-level voltage
VOL
Output off leakage current
IOFF
A
OSC1, OSC2: See figure 2
Note: 1 When the IOL values for the remaining output pins (when an arbitrary 4 output pins are excluded) are all under 1 mA. 2 Using the oscillator circuit in figure 1, when there is no power dissipation in the output pins, and when the input pins are at the VDD level. Ceramic Oscillator Guaranteed Constants
4 MHz ceramic oscillator CSA4. 00MG (Murata Mfg. Co., Ltd.) KBR4. 0M (Kyocera, Ltd.) C1, C2 30 pF 10% 30 pF 10%
Figure 1. Oscillator Circuit
Figure 2. Oscillator Stabilization Period
Figure 3. Reset Circuit
No.4789-7/17
LC7074, 7074M
RDS Data Processing System Organization Example
System Organization Example System Operation 1. Relationship between RDS Demodulated Data (LA2230 series IC output) and LC7074/M Output Data
* The DATA START signal indicated with broken lines is the signal when the D.S.CONTROL input is low level. * The serial data output (DATA OUT) from the LC7074/M is data that is delayed by one block with respect to the data received from the LA2230 series IC. * The ERROR and CORRECTION signals are output continuously when consecutive errors are detected. * The RECEIVE output signal is output only in periods when output data is being output from the DATA OUT pin. Relationship between the Demodulated Data and the Output Data
No.4789-8/17
LC7074, 7074M
2. Input Data Timing
* Input data is acquired on the falling edge of the input clock. * Input data must be stable just before and just after the falling edge of the input clock. This means that it is desirable that the input data change state on the rising edge of the input clock. Input Data Timing 3. Serial Data Output Format and Timing S E F OE OF A/B : Start bit (always "0") : Error flag } See table : Correction flag : Offset E : Offset F (always "0" : reserved for future expansion) : Group type version 0: Version A E and F Flags 1: Version B B1, B0 : Block number 00 : First block E F 01 : Second block No errors 0 0 10 : Third block Errors corrected 0 1 11 : Fourth block Uncorrectable errors 1 1 D0 to D15 : RDS data Note: When the CORR.SEL input pin is high level.
No.4789-9/17
LC7074, 7074M
Serial Data Output Format and Timing
No.4789-10/17
LC7074, 7074M
4. Informative Bits in the Serial Data Output * Error Flag (E) and Correction Flag (F) The error flag (E) and the correction flag (F) in the serial data output are identical to the ERROR and CORRECTION output pins, except that the logical levels are inverted. The meaning of the error and correction flags differ slightly depending on the setting that determines whether input data error correction is to be performed (the CORR.SEL pin). The tables below show the relations between the output value combinations of the error and correction flags. - When the CORR.SEL pin is high: Error correction enabled
Error flag (E) No errors Errors corrected Uncorrectable errors 0 0 1 Correction flag (F) 0 1 1 ERROR pin 1 1 0 CORRECTION pin 1 0 0
The value combination where E is 1 and F is 0 (or equivalently, where the ERROR pin is 0 and the CORRECTION pin is 1) cannot occur. - When the CORR.SEL pin is high: Error correction disabled
Error flag (E) No errors Uncorrectable errors 0 1 Correction flag (F) 0 1 ERROR pin 1 0 CORRECTION pin 1 0
The value combination where E is 1 and F is 0 (or equivalently, where the ERROR pin is 0 and the CORRECTION pin is 1) and where E is 0 and F is 1 (or equivalently, where the ERROR pin is 1 and the CORRECTION pin is 0) cannot occur. In this case, the combination indicating no errors is output if there were no errors in the data, and the combination indicating uncorrectable errors is output when there are errors in the data whether or not those errors are correctable.
* Offset E (OE) and Offset F (OF) When the IC has synchronized with the offset word E block data, the OE bit in the output data goes to "1". At this point the bits B1 and B0, which express the RDS block number, will be "00", i.e., both will be zero. The LC7074/M does not recognize an offset word F block as a correct offset word. Therefore, the OF bit in the output data will always be "0".
OE Bit Output
No.4789-11/17
LC7074, 7074M
* Block Number (B0 and B1) The block number bits indicate the data block of the output data.
B1 0 0 1 1 B0 0 1 0 1 Block First block (the offset word A block) Second block (the offset word B block) Third block (the offset word C or C' block) Fourth block (the offset word D block)
- The OE bit becomes one when the offset word E block data is output. At this point the bits B1 and B0 will be "00", i.e., both will be zero. - Consider the situation where there is a block in the RDS group data output for which the input data offset word cannot be detected. Here, the IC assumes that the blocks were input in the correct offset word order, and outputs B0 to B1 accordingly.
Block Number Output * Group Type Version (A/B) The A/B bit is set based on the third block offset word of input data. If the offset word is "C", the A/B bit is set to "0", and if the offset word is "C", the A/B bit is set to "1". Note that the version bit B0 in the second block (the offset word B block) data of input data is not used for group type version determination. As a result, the version bit A/B in the output data changes in the third block.
A/B Bit Output
No.4789-12/17
LC7074, 7074M
5. Group Synchronization * Recognized Offset Words The LC7074/M recognizes the five offset words A, B, C, C' and D. The offset word F, which is stipulated by the EBU, is not recognized. * Group Data Ordering and Synchronization The LC7074/M recognizes the following three types of group data. However, there is no limitation on the number of blocks in groups consisting of offset E blocks (type 3). (1) A - B - C - D (2) A - B - C' - D (3) E - E - E - E E-E-E E-E E As a result, there are nine block data orders (listed as (1) to (9) below) that the LC7074/M recognizes, and any other order is determined to be an error. Correct data orders (1) (2) (3) (4) (5) (6) (7) (8) (9) AB BC B C' CD C' D DA DE EE EA Data orders handled as errors AC BE EB * * *
The data input wait state is called a synchronization sequence. When a clock signal is first input to the LC7074/M from the demodulation IC, the LC7074/M starts the operation of detecting offset words from data synchronized with the clock. The LC7074/M synchronizes with the input data when it detects two blocks with correct offset words in correct positions. * Synchronization with RDS Group Data - RDS block data format
RDS Group Format
No.4789-13/17
LC7074, 7074M
- Synchronization with RDS data
* Here the LC7074/M detects blocks D and A consecutively. Since it synchronizes at A, output starts with B from the same group.
* Here the LC7074/M detects the D and B blocks. Since it synchronizes at B, output starts with A from the next group. RDS Synchronization Sequence * Synchronization with RDS/MMBS Group Data - RDS/MMBS compound group data format
RDS/MMBS Group Data Format - Synchronization with MMBS Group Data
* Detected for two consecutive blocks
* Detected for two of three blocks Note: The LC7074/M does not recognize that MMBS group data consists of four MMBS blocks (offset word E blocks). MMBS Synchronization Sequence
No.4789-14/17
LC7074, 7074M
* Pull-Out When a state occurs in which the LC7074/M is in the synchronized state and cannot detect the block data offset word, it enters a pull-out sequence. When the LC7074/M is unable to detect the offset word in five consecutive blocks while in a pull-out sequence, it goes to the pull-out state. When the LC7074/M pulls out, it stops clock and data output and switches to the synchronization sequence. Note that if the LC7074/M was unable to detect the offset word in fewer than five consecutive blocks, the synchronization state continues without change. - Pull-out in RDS group data
Note: "Error output" refers to the E and F flags in the output data and to the ERROR and CORRECTION pins. RDS Pull-Out Sequence - Pull-out in MMBS group data
MMBS Pull-Out Sequence
No.4789-15/17
LC7074, 7074M
6. Control Input Pin Read Timing (Pins CL.ED.SEL, CORR.SEL and D.S.CONTROL) * CL.ED.SEL The LC7074/M reads in the state of the CL.ED.SEL pin about 1 ms after a reset clear. It uses this signal for the internal settings that determine the clock output polarity.
CL. ED. SEL Pin Read-In Timing * CORR.SEL and D.S.CONTROL The LC7074/M continuously checks the state of these pins. As a result, error correction can be turned on or off and the DATA START signal output form can be changed at any time. - During synchronization detection (synchronization sequence) The pin states are read-in on each bit of demodulated data from the RDS demodulation IC (at the points shown by arrows in the figure). The state is read into the IC if the input values agree four times in a row.
Pin Read-In Timing during Synchronization Detection
No.4789-16/17
LC7074, 7074M
- Following synchronization detection (while synchronized) The LC7074/M reads in the pin state at the start of each block in the demodulated data from the RDS demodulation IC (at the points shown by arrows in the figure). The state is read into the IC if the input values agree four times in a row.
Pin Read-In Timing Following Synchronization Detection
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of August, 2001. Specifications and information herein are subject to change without notice.
PS No.4789-17/17

▲Up To Search▲

Price & Availability of LC7074M

	To Download LC7074M Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .